Route planning devices are well known in the field of navigational instruments. The method of route planning implemented by known prior art systems depends on the capabilities of system resources, such as processor speed and the amount and speed of memory. As increased system capability also increases system cost, the method of route planning implemented by a navigation device is a function of overall system cost.
One feature of increased system capability cost relates to route calculating algorithms. By their nature, route calculation algorithms are greedy algorithms that tend to be somewhat exponentially behaved in the sense that the bigger that a route network gets, the bigger the solutions base gets for finding a convergence between one location and another location. As used herein, the term convergence implies an attempt to connect a path, or a route between the two location points. The term solution is intended to imply a completed convergence. In other words, a solution, as used herein, implies a complete continuous path connecting the two location points. As one of ordinary skill in the art will understand upon reading this disclosure, there may be only one or many in-numerable solutions between two points. Alternatively stated, there can be few or many ways to find a convergence between the two locations.
From this description one can appreciate that as an algorithm executes in a convergence sequence, attempting to find a solution or path between two different locations within cartographic data, memory space is required to store the explored routes between those two locations. As the path network being processed becomes larger, the memory space required to store the explored routes between two locations likewise becomes larger. And additionally, the potential solutions base becomes larger.
In order to process route calculation algorithms with a suitable speed or efficiency, the processor executing the algorithm will require quick access to the memory space. Dynamic random access memory, or dynamic (RAM) as it is commonly referred to, is one form of quickly accessible memory which is frequently used in conjunction with a processor to execute algorithms. All routing algorithms need to have a suitable memory to keep track of status information of the locations explored, i.e. that it has visited in the network, as the route calculation algorithm executes. Again, as the path network being processed becomes larger, the necessary memory increases. Unfortunately, unlimited memory, RAM or otherwise, is not always available or suitable for a particular application, e.g. the particular device implementation. Thus, the ability of a route planning device to obtain solutions between two points using a route calculation algorithm is a function of available memory. And, the amount of memory that is required naturally has an impact on product cost.
One approach to route calculation algorithms is to arrange a route network in a sort of hierarchy so that the processor/memory system can operate on the primary thoroughfares in favor of more minor ones. Conventionally, a navigable network is comprised of roads, ferry routes, and possibly other means to travel from one location in the network to another. The navigable network is described as a collection of intersections (known as nodes) of navigable features and links, arcs or paths (road, ferry, etc.) connecting nodes. Thus, the navigable network is viewed as a collection of nodes where a travel direction decision might need to be made, and a collection of links or arcs connecting the nodes and describing a travel path from one node to another. The term adjacency is conventionally used to describe the travel path and nodes reachable in the network from a given node. A solution between two points in the network involves iteratively examining the adjacencies from the start and destinations in the network, eventually ‘discovering’ a low-cost path.
One limiting factor for the route calculation algorithm is the size of the navigable network. As an example, a connected network of all the roadways in the United States contains a very large number of nodes and possible pathways, more than any practical system can evaluate. The lowest layer (level 0) would typically contain all navigable features, from small residential roadways through major interstates. Level 1 might be defined to omit residential level roads, but include collector or arterial level roads up through major interstates. Additional levels are typically defined, with only the most major thoroughfares through a region (such as interstate highways) defined at the highest routing level. Each level is conventionally defined to result in a fully connected network. The number of navigable features at level 0 is very large, as is the solution space for a routing algorithm operating only at level 0. Upper level networks contain far fewer navigable features, allowing the solution space to decrease dramatically.
Many conventional routing algorithms take advantage of this layering by first searching at the lowest defined layer (conventionally layer 0), and then switching to upper level layers as a function of implementation-specific switching criteria. As the algorithm progresses it conventionally seeks to switch from lower to higher layers, eventually searching only in the highest defined layer, which affords route traversal across large distances within a comparatively small solution space. Of course, a suitable solution may be found prior to reaching the highest routing level. It is through this approach that a system with limited search resources is able to obtain a good, though not necessarily optimal, solution from a very large solution space. Algorithms of this sort are conventionally bidirectional, searching simultaneously from the start and target locations in the routing network.
Almost all practically implemented routing algorithms use this hierarchical approach in order to afford an obtainable solution for any processor/memory system that has a limited amount of memory and a limited amount of computing power.
Many contemporary systems use a minimum of one to two megabytes (MB) of dynamic memory storage capacity to obtain solutions between two points of cartographic data using conventional route calculation algorithms. Comparatively speaking, 2 megabytes of memory is a lot of memory and is a luxury which is not always realizable in compact, low power device implementations such as handheld or portable devices. Even with 2 megabytes of RAM no routing algorithm can even begin to explore every path in a large thoroughfare network; that would require Gigabytes of memory. Additionally, exhaustively exploring every adjacency at every hierarchal level, even with unlimited memory, is not an effective use of a system's resources.
Indeed, some conventional processor/memory systems attempt to obtain solutions in a minimized memory storage space, e.g. using around 512 Kilobytes of RAM. However, such conventional systems frequently do not result in very good solutions. That is, those conventional systems may provide a solution between the two points. But, the solution will not include a best or even reasonably best path between the two locations when weighing all of the relevant criteria, e.g. shortest path, fastest path, path classification and so forth, due to their conventional algorithm approaches.
In summary, current prior art systems have created a spectrum of products in which the degree of navigational accuracy is dictated primarily by the cost of the system. The lower cost systems currently offer a low degree of accuracy that is often inadequate for users. Therefore, there exists a need for a navigational route planning device which is more efficient and accurate than current low cost systems, without requiring more expensive system resources. In addition, there is also a need for a navigational route planning device which provides more efficient use of memory and other resources in connection with a route calculation algorithm and which quickly obtains a best or reasonable best path between two locations.